1. Field of the Invention
The present invention relates to integrated circuits and in particular to methods of testing the integrity of electrical connection of such circuits to external equipment.
2. Background Information
In order to achieve greater reliability and performance of integrated circuitry, it has become desirable to pack as many functions as possible onto a single chip. This is because internal chip connections are inherently more reliable than externally wired connections and because signal speed is greater within a chip than between chips. Additionally, the lower the number of chips and the higher their density, the more chips (and consequently more overall function) can be accommodated on a product printed circuit board.
So called ASICs (Application Specific Integrated Circuits) are one well established approach to this end. In an ASIC, many standard logic functions, memory and sometimes a CPU are provided by a vendor on one chip. The interconnections between these standard components are then customized by an application developer to produce an application specific chip. The interconnections are defined by programming, using Hardware Definition Language (HDL), and then applied to the chip customizing and manufacturing process.
Also known, particularly for prototyping ASIC designs or as simpler alternatives are FPGAs (Field Programmable Gate Arrays). As the name implies, FPGAs can be programmed in the field as well as in development.
As in any development activity, the testing of circuits under development is an important aspect and is traditionally carried out by monitoring signals generated during operation. However, this becomes increasingly difficult as circuit densities increase and more function is packed into a single chip because there are more operational signals to test. Additionally, many of the signals it is desired to test are increasingly inaccessible as they only occur internally of the chip and are not present at the normal output points through which the chip is functionally connected to other components on the PCB.
U.S. Pat. No. 6,311,303 B1 to Gates et al. (Adaptec, Inc.) for a “Monitor Port with Selectable Trace Support” shows the provision of a monitor port in an integrated circuit through which signals from a large number of modular internal components can be selectively provided to an external monitor process. A Select Register is loaded to determine which signals are outputted from the monitor port. The register controls either tri-state buffers at each module or a shared multiplexer to gate the desired signals to the port.
Currently, in the development of ASICs, a similar debug port is provided through which internal signals can be selectively multiplexed out to connector pins or other contacts on a test or product PCB. Probes from a logic analyzer can then be connected to these pins to monitor the ASIC internal signals during a test run. The status of these signals during a test run can be recorded by the logic analyzer for diagnostic purposes to facilitate debugging of the circuit design.
ASIC debug ports may allow many internal signals to be multiplexed out to the diagnostic connector at any one time (a typical bus width can be 64 signals or upwards). Thus the diagnostic connector must have enough signal pins to cope including enough pins to be allocated for signal ground (essential for signal integrity when connecting to the logic analyzer). However, being used only for diagnostics, PCB designers will not devote much board real estate to accommodate large diagnostic connectors when that space could be used to populate other components which are essential for the functionality of the product PCB. Therefore, diagnostic connectors must be dense in order to pack in as many pins as possible for a given board area.
Smaller connectors mean less mechanical contact area is available when mating with a logic analyzer probe. This can affect the signal integrity of the ASIC signals being monitored. This problem is exacerbated by the fact that logic analyzer probes are getting larger and heavier due to the amount of termination circuitry that must be included to measure signals of higher and higher frequencies. They are also getting denser and denser in order to be able to monitor more and more signals. Larger probes cause more mechanical strain when they are attached to the diagnostic connector increasing the chances of bad contact and therefore loss of ASIC diagnostic information. The PCB being tested may also be integrated into a larger electronic system which means that the amount of mechanical space that allows access to the connector may be limited. This can also lead to the logic analyzer probes not being mated properly to the connector, in turn affecting signal integrity.
Another cause of loss of signal integrity can be due to wear and tear of logic analyzer probes and cables, or wear and tear of the diagnostic connector through repeated use.
These problems and various suggested connection techniques to minimize them are discussed in an article “Physical Connections are Key in FPGA Debug” by B. J. LaMeres of Agilent Technologies published in COTS Journal Online, June 2004).
However, there is still a problem of reduced signal integrity as smaller, more densely packed connectors are used to enable more signals to be monitored with minimum usage of PCB real estate. This can result in a signal appearing to be stuck at one continuous value, whereas, in fact it is simply the mechanical connection which has failed. The logic analyzer or engineer examining a signal trace may incorrectly interpret this as implying a particular circuit or design failure.
The current approach to this problem is to set up the logic analyzer and PCB, perform a test run, and record the signals from the debug port. From knowledge of the ASIC inner workings the development engineer should know which signals being monitored are expected to transition (either from high to low or low to high) during a run. If a signal which should be transitioning remains stuck at low (or high) then the connection for that signal may have been compromised for the mechanical reasons stated above. However, another reason why the signal is not transitioning may be because there is a functional problem with the ASIC that the engineer is trying to investigate. A disadvantage of this approach is, that the engineer may be unable to tell if the non-transitioning signal is due to a mechanical problem with the diagnostics connector or a functional problem with the ASIC. In depth knowledge of the ASIC design being tested is required for an engineer to make an educated decision between the two possibilities.